Implements PCIe 6.0 feature set with optimized power, area and latency, data security with integrated IDE engine, and supports Endpoint, Root-Port, Dual-Mode and Switch port configurations.
Rambus Inc. announced the availability of its PCIe 6.0 controller.
PCIe 6.0 controller block diagram
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The PCIe spec is the interconnect of choice across a landscape of data-intensive markets including data center, AI/ML, HPC, automotive, IoT, defense and aerospace. Optimized for power, area and latency, the PCIe 6.0 controller delivers data rates up to 64GT/s (Gigatransfers per second) for high-performance applications. In addition, the controller provides security with an Integrity and Data Encryption (IDE) engine that monitors and protects PCIe links vs. physical attacks.
“The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power and area,” said Sean Fan, COO. “As the latest addition to our portfolio of industry-leading interface IP, our PCIe 6.0 Controller offers customers an easy to integrate solution that delivers both performance and security for advanced SoCs and FPGAs.“
Key features of Rambus PCIe 6.0 controller include:
- Supports PCIe 6.0 spec including 64GT/s data rate and PAM4 signaling
- Supports fixed-sized FLITs that enable high-bandwidth efficiency
- Implements low-latency Forward Error Correction (FEC) for link robustness
- Internal data path size automatically scales up or down (256, 512, 1,024 bits) based on maximum link speed and width for reduced gate count and optimal throughput
- Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1
- Supports Endpoint, Root-Port, Dual-Mode and Switch port configurations
- Integrated IDE optimized for performance
Resources:
Rambus PCIe 6.0 controller DS (registration required)
Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0 WP (registration required)
